A 3D package may contain two or more chips (integrated circuits (ICs)) stacked vertically so that they occupy less floor space and/or have greater connectivity. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is used, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking).
Heat dissipation is increasingly problematic for high end chips that use die stacking. In particular, stacking two or more chips may lead to localized thermal hot spots. As the localized thermal hot spots are embedded in the stack-up, this may reduce the ability to cool the hot spots and achieve low junction temperatures. Conventional cooling solutions for achieving low junction temperatures include heat sinks, heat spreaders, and/or improved printed circuit boards. Conventional techniques of simply increasing the size of the heat spreader and/or the heat sink are impractical in small form factor devices (e.g., Smartphones).